Historically, the emitter region of a bipolar transistor was formed by implanting or diffusing dopant into a single crystal base region previously formed on an underlying substrate. However, in the last several years implants and diffusions have been replaced with a method whereby doped polysilicon is used as a dopant source to form an underlying emitter region.
According to this method, a doped polysilicon structure is formed above the base region. The dopant is then driven-in with heat such that the dopant diffuses downward, penetrating into the underlying base. This diffusion of dopant from the polysilicon into the single crystal substrate forms a very shallow and a very abrupt emitter-base junction. Further, this method of forming an emitter region using a doped polysilicon dopant source is advantageously compatible with existing metal-oxide-silicon ("MOS") and bipolar metal-oxide-silicon ("BiCMOS") fabrication processes.
This prior art formation of an emitter region is depicted in FIGS. 1A-1D. FIG. 1A depicts a preliminary stage in the formation of a bipolar transistor on a single crystal substrate or wafer 2. Initially, a collector region 4 and buried layer region 6 are formed, after which the base region 8 is formed of an opposite polarity dopant.
Overlying the single crystal collector and base regions will be a relatively thick (50 .ANG. to 1,000 .ANG.) layer 10 of oxide, or perhaps nitride. Often layer 10 will be silicon dioxide, SiO.sub.2, a compound that always forms automatically with silicon that is exposed to oxygen and/or moisture. Alternatively, layer 10 may be a nitride layer, e.g., Si.sub.3 N.sub.4, that was deposited to protect the underlying regions shown in FIG. 1A during processing of other devices on the same substrate. For example, where substrate 2 includes MOS devices, a nitride layer 10 is usually formed to protect the underlying bipolar transistor region while etching away the MOS device gate oxide.
Before a doped polysilicon structure can be formed atop the base region 8, the oxide or nitride layer 10 must be removed. If layer 10 were allowed to remain, it would interfere with the formation of the emitter-base interface. More specifically, the continued presence of an oxide or nitride layer 10 would contribute an unacceptably large equivalent resistance in series with the emitter junction. This resistance is shown symbolically in FIG. 1D as R.
According to the prior art and as depicted in FIG. 1B, the oxide or nitride layer 10 is removed by wetting the entire structure with hydrofluoric acid, and then rinsing the structure. Although the acid wet dip will remove layer 10, unfortunately the moment the wafer is dry and exposed to air a new native oxide layer 12 forms, as depicted in FIG. 1B. Typically the new layer oxide 12 will only be about 3 .ANG. to 4 .ANG. thick, approximately the diameter of a molecule. Oxide layer 12 inevitably forms because silicon is a self-passivating material that reacts with oxygen to form SiO.sub.2.
As shown in FIG. 1C, a region of doped polysilicon 14 is next deposited over the base region 8, but unfortunately is separated therefrom by the few angstrom thick layer 12. The doped polysilicon structure 14 is then driven in with heat, whereupon the dopant (which is the same polarity type as that of the collector region 4) diffuses downward to form the emitter region 16. FIG. 1C depicts the fabrication process after this driving-in step has occurred.
However, because the dopant from the doped polysilicon structure 14 was separated from the base region 8 by the oxide layer 12, an equivalent base-emitter series resistance R of perhaps 200.OMEGA. to 300.OMEGA. results, as shown in FIG. 1D. In most applications, an emitter-base series resistance of a few hundred ohms severely degrades the performance of transistor 2.
According to the prior art, the above-described series resistance is present whenever a single crystal silicon structure interfaces with a region of deposited silicon, or amorphous silicon. Because the interface will always be separated by a few angstrom of native oxide, there will always be a resultant series resistance across the interface of several hundred ohms.
What is needed is a method for fabricating such interfaces without the formation of an inherent, relatively large series interface resistance. More particularly, what is needed in fabricating a bipolar transistor is a method of forming the emitter using a doped polysilicon dopant source, without the presence of a native oxide layer 12. Such method should be compatible with existing bipolar and BiCMOS fabrication sequences, and should result in a series resistance of a few ohms or so. The present invention describes such a method.